The Advanced Encryption Standard (AES), also known as Rijndael, is a block cipher developed by two Belgian cryptographers, Joan Daemen and Vincent Rijmen and adopted as an encryption standard by the United States government. AES was announced in Nov. 26, 2001 by the National Institute of Standards and Technology (NIST) as U.S. FIPS PUB 197 (FIPS 197).
AES has a fixed block size of 128 bits and a key size of 128, 192 or 256 bits. Key expansion using Rijndael's key schedule transforms the keys of size 128, 192 or 256 bits into 10, 12 or 14 round keys of 128 bits. The round keys are used to process the plaintext data in rounds as 128-bit blocks (viewed as 4-by-4 arrays of bytes) and convert them to ciphertext blocks. Typically, for a 128-bit input to the round (16 bytes) each byte is replaced by another byte according to a lookup table called the S-box. This portion of the block cipher is called SubBytes. Next the rows of bytes (viewed as a 4-by-4 array) are cyclically shifted or rotated left by a particular offset (i.e. row zero by 0 bytes, row one by 1 byte, row two by 2 bytes and row three by 3 bytes). This portion of the block cipher is called ShiftRows. Then each of the columns of bytes are viewed as four coefficients of a polynomial in a finite field, GF(256) (also called Galois field 28), and multiplied by an invertible linear transformation. This portion of the block cipher is called MixColumns. Finally, the 128-bit block is XORed with a round key to produce a ciphertext block of 16 bytes, which is called AddRoundKey.
On systems with 32-bit or larger words, it is possible to implement the AES cipher by converting the SubBytes, ShiftRows and MixColumns transformations into four 256-entry 32-bit tables, which utilize 4096 bytes of memory. One drawback to a software implementation is performance. Software runs orders of magnitude slower than devoted hardware so it is desirable to have the added performance of a hardware/firmware implementation.
Typical straightforward hardware implementations using lookup memories, truth tables, binary decision diagrams or 256 input multiplexers are costly in terms of circuit area. Alternative approaches using finite fields isomorphic to GF(256) may be efficient in area but may also be slower than the straightforward hardware implementations. Thus options that provide efficient space-time design tradeoffs have not been fully explored.